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| (R) SP6654 Ideal for portable designs powered with Li Ion battery High Efficiency 800mA Synchronous Buck Regulator FEATURES Ultra-low 20A Quiescent Current 98% Efficiency Possible 800mA Output Current 2.7V to 5.5V Input Voltage Range Output Adjustable Down to 1.0V No External FET's Required 1.25A Inductor Peak Current Limit 100% Duty Ratio Low Dropout Operation 80A Light Load Quiescent Current in Dropout Logic Shutdown Control Programmable UVLO Small 10pin MSOP Package Power Good Indicator Industry Standard 10 Pin MSOP and and Small DFN Package PV IN V IN PWR GD D1 D0 1 2 3 4 5 10 LX SP6654 10 Pin DFN 9 PGND 8 GND 7 VOUT 6 FB Now Available in Lead Free Packaging APPLICATIONS PDA's DSC's MP3 Players USB Devices Point of Use Power DESCRIPTION The SP6654 is a 800mA synchronous buck regulator which is ideal for portable applications that use a Li-Ion or 3 cell alkaline/NiCD/NiMH input. The SP6654's proprietary control loop, 20A light load quiescent current, and 0.3 power switches provide excellent efficiency across a wide range of output currents. As the input battery supply decreases towards the output voltage the SP6654 seamlessly transitions into 100% duty ratio operation further extending useful battery life. The SP6654 is protected against overload and short circuit conditions with a precise inductor peak current limit. Other features include programmable under voltage lockout, externally programmed output voltage down to 1.0V, logic level shutdown control, and an open drain power good indicator when VOUT is above 94% of its programmed value. TYPICAL APPLICATION SCHEMATIC 2.7V to 5.5V Input VI L1 10H 10 RVIN CVIN 1F VOUT 800mA VO CIN 22F 1M SP6654 PVIN VIN PWRGD LX PGND GND VOUT FB COUT 22F CF RF 22pF PWRGD D1 D0 D1 D0 RI 200K Date: 05/25/04 SP6654 High Efficiency 800mA Synchronous Buck Regulator (c) Copyright 2004 Sipex Corporation 1 ABSOLUTE MAXIMUM RATINGS PVIN,VIN .............................................................................................. 6V All other pins .............................................................. -0.3V to VIN+0.3V PVIN, PGND, LX current ........................................................................ 2A Storage Temperature .................................................. -65 C to 150 C Operating Temperature ................................................. -40C to +85C Lead Temperature (Soldering, 10 sec) ....................................... 300 C These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. ELECTRICAL CHARACTERISTICS VIN=PVIN=VSDN=3.6V, VOUT=VFB, IO = 0mA, TAMB = -40C to +85C, The denotes the specifications wich apply over the full operating temperature range, unless otherwise specified. PARAMETER Input Voltage Operating Minimum Output Voltage FB Set Voltage, Vr MIN UVLO 1.0 0.784 0.800 0.816 4 Overall Accuracy 5 On-Time Constant - KON Min, TON=KON/(VIN-VOUT) Off-Time Min, TOFF=KOFF/VOUTConstant K OF F Off-Time Blanking PMOS Switch Resistance NMOS Switch Resistance Inductor Current Limit LX Leakage Current 1.0 1.5 2.25 3.0 V*s % TYP MAX 5.5 UNITS V V V CONDITIONS Result of IQ measurement at VIN=PVIN=5.5V FB Set Voltage, Vr 25 C, IO=200mA Close Loop. LI = 10H, Measured at VIN=5.5V, no load, TAMB = 0 C to 70 C Measured at VIN=3.6V, 200mA load, Close Loop Close Loop, LI = 10H, COUT = 22F Inductor current limit tripped, VFB=0.5V Measured at VOUT = 2V TAMB=27 C 1.6 2.4 100 0.3 0.3 1.25 0.01 96 3.2 ns 0.6 0.6 1.50 3 V*s A A IPMOS = 200mA INMOS = 200mA VFB=0.5V D0=D1=0 VOUT=2.5V, IO=200mA TAMB=27 C Power Efficiency 92 Minimum Guaranteed Load Current VIN Quiescent Current VIN Shutdown Current VOUT Quiescent Current VOUT Shutdown Current 2.55 UVLO Undervoltage Lockout Threshold, VIN falling 2.70 2.85 UVLO hysteresis PWRGD Low Output Voltage PWRGD Leakage Current PWRGD Rising Threshold PWRGD Hysterisis D1,D0 Leakage Current 0.60 D1,D0 Input Threshold Voltage 1.25 FB Leakage Current 1 1.8 100 -6 80 1 0.90 500 800 900 20 1 2 1 2.70 2.85 3.00 40 0.4 1 30 500 5 500 2.85 3.00 3.15 % VOUT=3.3V, IO=800mA TAMB=27 C mA A nA A nA VOUT=3.3V, VIN=3.6V and VIN= 5.5V D1=D0=0V VOUT = 3.3V D1=D0=0V D1=0V, D0=VIN D1=VIN, D0=0V D1=VIN, D0=VIN TAMB=27 C V mV V A % mV nA VIN=3.3V, ISINK=1mA VPWRGD =3.6V FB Set Voltage -6%, TAMB=27 C TAMB=27 C High to Low Transition Low to High Transition FB=1V V nA Date: 05/25/04 SP6654 High Efficiency 800mA Synchronous Buck Regulator (c) Copyright 2004 Sipex Corporation 2 PIN DESCRIPTION PIN NUMBER 1 2 3 PIN NAME PVIN VIN PWRGD DESCRIPTION Input voltage power pin. Inductor charging current passes through this pin. Internal supply voltage. Control circuitry powered from this pin. Open drain Power Good indicator. If VFB is less than 750mV this pin is pulled to ground. When VFB is above 750mV this pin is open. Connect a resistor from this pin to VIN or VOUT to create a logic signal. Digital mode control input. See table I for definition. Digital mode control input. See table I for definition. External feedback network input connection. Connect a resistor from FB to ground and FB to VOUT to set the output voltage. This pin regulates to the internal bandgap reference voltage of 0.8V. Output voltage sense pin. Used by the timing circuit to set minimum on and off times. Internal ground pin. Control circuitry returns current to this pin. Power ground pin. Synchronous rectifier current returns through this pin. Inductor switching node. Inductor tied between this pin and the output capacitor to create regulated output voltage. 4 5 6 D1 D0 FB 7 8 9 10 VOUT GND PGND LX D1 0 0 1 1 D0 0 1 0 1 Shutdown. All internal circuitry is disabled and the power switches are opened. Device enabled, falling UVLO threshold =2.70V Device enabled, falling UVLO threshold =2.85V Device enabled, falling UVLO threshold =3.00V Table 1. Operating Mode Definition FUNCTIONAL DIAGRAM Vin DRVON VOLOW TONOVER MIN Ton Internal Supply TONOVER Vos VOLOW REF + -REF' + VRAMP Min Ton Min Ton = KON/(VIN -VOUT) M DRVON R S Q VOUT PVIN 1 OVR_I + DRIVER - C ILIM/M - C _ Q FB + - FB' RST OVR_I LX DRVON REF Ref Block UVLO TSD D0 D1 + One-Shot =100ns BLANK - C Zero_X PGND TOFF = KOFF/VOUT ILIM/M OVR_I 750mV GND + C PWRGD DRVON BLANK BLANK = Tblank(=100ns) or Toff = Koff/Vout FB UVLO Date: 05/25/04 SP6654 High Efficiency 800mA Synchronous Buck Regulator (c) Copyright 2004 Sipex Corporation 3 TYPICAL PERFORMANCE CHARATERISTICS Refer to the typical application schematic, TAMB= +27C 100 95 90 100 95 90 Efficiency (%) Vi=3.6V Vi=3.9V Vi=4.2V Vi=5.0V 1.0 10.0 ILoad (mA) 100.0 1000.0 Efficiency (%) 85 80 75 70 65 60 0. 85 80 75 70 65 60 0.1 Vi=3.6V Vi=3.9V Vi=4.2V Vi=5.0V 1.0 10.0 ILoad (mA) 100.0 1000.0 Figure 1. Efficiency vs Load, VOUT = 3.3V Figure 2. Efficiency vs Load, VOUT = 1.5V 3.40 Vi=3.6V Vi=3.9V Vi=4.2V Vi=5.0V 1.55 Vi=3.6V Vi=3.9V Vi=4.2V Vi=5.0V 3.35 Vout (V) 1.53 1.51 3.30 Vout (V) 1.49 3.25 1.47 3.20 0 200 400 600 ILoad (mA) 800 1000 1.45 0 200 400 600 800 1000 ILoad (mA) Figure 3. Line/Load Rejection, VOUT = 3.3V Figure 4. Line/Load Rejection, VOUT = 1.5V 500 Tamb = 85C Tamb = 25C Tamb = -40C 400 50 Tamb = 85C Tamb = 25C Tamb = -40C 40 Iin (uA) Iin (A) 300 30 200 20 100 10 0 3.0 3.3 3.6 Vin (V) 3.9 4.2 0 3.0 3.3 3.6 Vin (V) 3.9 4.2 Figure 5. No Load Battery Current, VOUT=3.3V Figure 6. No Load Battery Current, VOUT=1.5V Date: 05/25/04 SP6654 High Efficiency 800mA Synchronous Buck Regulator (c) Copyright 2004 Sipex Corporation 4 TYPICAL PERFORMANCE CHARATERISTICS: Continued Refer to the typical application schematic, TAMB= +27C 3.5 3.0 2.5 3.5 3.0 2.5 Kon (V*usec) Kon (V*usec) 2.0 1.5 1.0 0.5 0.0 3.6 2.0 1.5 1.0 0.5 3.9 4.2 4.5 Vin (V) 4.8 5.1 5.4 0.0 3.0 3.3 3.6 3.9 4.2 4.5 Vin (V) 4.8 5.1 5.4 Figure 7. KON vs VIN, VOUT=3.3V Figure 8. KON vs VIN, VOUT=1.5V 3.5 3.0 2.5 Koff (V*usec) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 3.6 Koff (V*usec) 2.0 1.5 1.0 0.5 3.9 4.2 4.5 Vin (V) 4.8 5.1 5.4 0.0 3.0 3.3 3.6 3.9 4.2 Vin (V) 4.5 4.8 5.1 5.4 Figure 9. KOFF vs VIN, VOUT=3.3V Figure 10. KOFF vs VIN, VOUT=1.5V 700.0 700.0 600.0 600.0 500.0 500.0 Frequency (KHz) 400.0 Frequency (KHz) 400.0 300.0 300.0 200.0 Vout = 3.3V Measured Vout = 3.3V Calculated 4.0 Vin (V) 4.5 5.0 200.0 Vout = 1.5V Measured Vout = 1.5V Calculated 3.4 3.8 4.2 Vin (V) 4.6 5.0 100.0 100.0 0.0 3.5 0.0 Figure 11. Ripple Frequency vs. VIN, IOUT=600mA, VOUT=3.3V Date: 05/25/04 Figure 12. Ripple Frequency vs. VIN, IOUT=600mA, VOUT=1.5V (c) Copyright 2004 Sipex Corporation SP6654 High Efficiency 800mA Synchronous Buck Regulator 5 TYPICAL PERFORMANCE CHARATERISTICS: Continued Refer to the typical application schematic, TAMB= +27C CH.1=VIN 2.5V/div CH.2=VOUT 2.0V/div CH.1=VIN 2.5V/div CH.2=VOUT 5.0V/div CH.4=IIN 0.5A/div CH.4=IIN 0.5A/div Figure 13. VIN Start up, IOUT=0.6A, VOUT=3.3V Figure 14. VIN Start up, IOUT=0.6A, VOUT=1.5V CH.2=VOUT 50mV/div. AC CH.2=VOUT 50mV/div. AC CH.4=IOUT 0.5A/div CH.4=IIN 0.5A/div Figure 15. Load Step, IOUT=0.4A to 0.8A, VOUT=3.3V Figure 16. Load Step, IOUT=0.4A to 0.8A, VOUT=1.5V CH.1=VSHDN 10V/div. CH.1=VSHDN 10V/div. CH.2=VOUT 1V/div. AC CH.2=VOUT 2V/div. AC CH.4=ILx 0.5A/div CH.4=ILx 0.5A/div Figure 17. Start up from SHDN, IOUT=0.6A, VOUT=3.3V Date: 05/25/04 Figure 18. Start up from SHDN, IOUT=0.6A, VOUT=1.5V (c) Copyright 2004 Sipex Corporation SP6654 High Efficiency 800mA Synchronous Buck Regulator 6 OPERATION The SP6654 is a high efficiency synchronous buck regulator with an input voltage range of +2.7V to +5.5Vand an output that is adjustable between +1.0V and VIN. The SP6654 features a unique on-time control loop that runs in discontinuous conduction mode (DCM) or continuous conduction mode (CCM) using synchronous rectification. Other features include, over-current protection, digitally controlled enable and under-voltage lockout, an external feedback pin, and a power good indicator. The SP6654 operates with a light load quiescent current of 20A using a 0.3 PMOS main switch and a 0.3 NMOS synchronous switch. It operates with excellent efficiency across the entire load range, making it an ideal solution for battery powered applications and low current step-down conversions. The part smoothly transitions into a 100% duty cycle under heavy load/ low input voltage conditions. On-Time Control - Charge Phase RAMP: CCM OPERATION DRVON I(L1) REF, FB FB' VOS REF' RAMP: DCM OPERATION DRVON I(L1) FB' REF' REF, FB VOS The SP6654 uses a precision comparator and a minimum on-time to regulate the output voltage and control the inductor current under normal load conditions. As the feedback pin drops below the regulation point, the loop comparator output goes high and closes the main switch. The minimum on-timer is triggered, setting a logic high for the duration defined by: TON = where: KON = 2.25V*sec constant VIN = VIN pin voltage VOUT = VOUT pin voltage To accommodate the use of ceramic and other low ESR capacitors, an open loop ramp is added to the feedback signal to mimic the inductor current ripple. The following waveforms describe the ideal ramp operation in both CCM and DCM operation. In either CCM or DCM, the negative going ramp voltage (VRAMP in the functional diagram) KON VIN - VOUT is added to FB and this creates the FB's signal. This FB signal is applied to the negative terminal of the loop comparator. To the positive terminal of the loop comparator is applied the REF voltage of 0.8V plus an offset voltage Vos to compensate for the DC level of VRAMP applied to the negative terminal. The result is an internal ramp with enough negative going offset (approximately 50mV) to trip the loop comparator whenever FB falls below regulation. The output of the loop comparator, a rising VOLOW, causes a SET if BLANK = 0 and OVR_I = 0. This starts inductor charging (DRVON = 1) and starts the minimum on-timer. The minimum on-timer times out and indicates DRVON can be reset if the voltage loop is satisfied. If VOUT is still below the regulation point RESET is held low until VOUT is above Date: 05/25/04 SP6654 High Efficiency 800mA Synchronous Buck Regulator (c) Copyright 2004 Sipex Corporation 7 OPERATION: Continued regulation. Once RESET occurs TON minimum is reset, and the TOFF one-shot is triggered to blank the loop comparator from starting a new charge cycle for a minimum period. This blanking period occurs during the noisy LX transition to discharge, where spurious comparator states may occur. For TOFF > TBLANK the loop is in a discharge or wait state until the loop comparator starts the next charge cycle by DRVON going high. If an over current occurs during charge the loop is interrupted and DRVON is RESET. The offtime one-shot pulse width is widened to TOFF = KOFF / VOUT, which holds the loop in discharge for that time. At the end of the off-time the loop is released and controlled by VOLOW. In this manner maximum inductor current is controlled on a cycle-by-cycle basis. An assertion of UVLO (undervoltage lockout) or TSD (thermal shutdown) holds the loop in no-charge until the fault has ended. On-Time Control - Discharge Phase L = Inductor value IOUT = Load current RCH = PMOS on resistance, 0.3 typ. If the IOUT * RCH term is negligible compared with (VIN - VOUT), the above equation simplifies to: ILR KON L For most applications, the inductor current ripple controlled by the SP6654 is constant regardless of input and output voltage. Because the output voltage ripple is equal to: VOUT (ripple) = ILR * RESR where: RESR = ESR of the output capacitor the output ripple of the SP6654 regulator is independent of the input and output voltages. For battery powered applications, where the battery voltage changes significantly, the SP6654 provides constant output voltage ripple throughout the battery lifetime. This greatly simplifies the LC filter design. The maximum loop frequency in CCM is defined by the equation: FLP (VIN - VOUT) * (VOUT + IOUT * RDC) KON * [VIN + IOUT * (RDC - RCH)] The discharge phase follows with the high side PMOS switch opening and the low side NMOS switch closing to provide a discharge path for the inductor current. The decreasing inductor current and the load current cause the output voltage to drop. Under normal load conditions when the inductor current is below the programmed limit, the off-time will continue until the output voltage falls below the regulation threshold, which initiates a new charge cycle via the loop comparator. The inductor current "floats" in continuous conduction mode. During this mode the inductor peak current is below the programmed limit and the valley current is above zero. This is to satisfy load currents that are greater than half the minimum current ripple. The current ripple, ILR, is defined by the equation: ILR KON L * VIN - VOUT - IOUT * RCH VIN - VOUT where: FLP = CCM loop frequency RDC = NMOS on resistance, 0.3 typ. Ignoring conduction losses simplifies the loop frequency to: FLP 1 KON * VOUT VIN * (VIN - VOUT) where: AND'ing the loop comparator and the on-timer reduces the switching frequency for load currents below half the inductor ripple current. This increases light load efficiency. The minimum on-time insures that the inductor current ripple is a minimum of KON/L, more than the load Date: 05/25/04 SP6654 High Efficiency 800mA Synchronous Buck Regulator (c) Copyright 2004 Sipex Corporation 8 OPERATION: Continued current demands. The converter goes in to a standard pulse frequency modulation (PFM) mode where the switching frequency is proportional to the load current. Low Dropout and Load Transient Operation AND'ing the loop comparator also increases the duty ratio past the ideal D= VOUT /VIN up to and including 100%. Under a light to heavy load transient, the loop comparator will hold the main switch on longer than the minimum on timer until the output is brought back into regulation. Also, as the input voltage supply drops down close to the output voltage, the main MOSFET resistance loss will dictate a much higher duty ratio to regulate the output. Eventually as the input voltage drops low enough, the output voltage will follow, causing the loop comparator to hold the converter at 100% duty cycle. This mode is critical in extending battery life when the output voltage is at or above the minimum usable input voltage. The dropout voltage is the minimum (VIN -VOUT) below which the output regulation cannot be maintained. The dropout voltage of SP6654 is equal to IL* (0.3+ RL1) where 0.3 is the typical RDS(ON) of the P-Channel MOSFET and RL is the DC resistance of the inductor. The SP6654 has been designed to operate in dropout with a light load Iq of only 80A. The on-time control circuit seamlessly operates the converter between CCM, DCM, and low dropout modes without the need for compensation. The converter's transient response is quick since there is no compensated error amplifier in the loop. Inductor Over-Current Protection with a second voltage drop representing the maximum allowable inductor current. As the two voltages become equal, the over-current comparator triggers a minimum off-time one shot. The off-time one shot forces the loop into the discharge phase for a minimum TOFF time causing the inductor current to decrease. At the end of the off-time, loop control is handed back to the AND'd on-time signal. If the output voltage is still low, charging begins until the output is in regulation or the current limit has been reached again. During startup and overload conditions, the converter behaves like a current source at the programmed limit minus half the current ripple. The minimum TOFF is controlled by the equation: TOFF (MIN) = KOFF VOUT Under-Voltage Lockout The SP6654 is equipped with a programmable under-voltage lockout to protect the input battery source from excessive currents when substantially discharged. When the input supply is below the UVLO threshold both power switches are open to prevent inductor current from flowing. The three levels of falling input voltage UVLO threshold are shown in Table 1, with a typical hysteresis of 120mV to prevent chattering due to the impedance of the input source. During UVLO, PWRGD is forced low. Under-Current Detection To reduce the light load dropout Iq, the SP6654 over-current system is only enabled when IL1 > 400mA. The inductor over-current protection circuitry is programmed to limit the peak inductor current to 1.25A. This is done during the ontime by comparing the source to drain voltage drop of the PMOS passing the inductor current Date: 05/25/04 The synchronous rectifier is comprised of an inductor discharge switch, a voltage comparator, and a driver latch. During the off-time, positive inductor current flows into the PGND pin 9 through the low side NMOS switch to LX pin 10, through the inductor and the output capacitor, and back to pin 9. The comparator monitors the voltage drop across the discharge NMOS. As the inductor current approaches zero, the channel voltage sign goes from negative to positive, causing the comparator to trigger the driver latch and open the switch to prevent (c) Copyright 2004 Sipex Corporation SP6654 High Efficiency 800mA Synchronous Buck Regulator 9 OPERATION: Continued inductor current reversal. This circuit along with the on-timer puts the converter into PFM mode and improves light load efficiency when the load current is less than half the inductor ripple current defined by KON/L. Shutdown/Enable Control current to ground. Tying a resistor from pin 3 to VIN or VOUT creates a logic level power good indicator. PWRGD is forced low when in UVLO. External Feedback Pin The D0, D1 pins 4,5 of the device are logic level control pins that according to Table 1 shut down the converter when both are a logic low, or enables the converter when either are a logic high. When the converter is shut down, the power switches are opened and all circuit biasing is extinguished leaving only junction leakage currents on supply pins 1 and 2. After pins 4 or 5 are brought high to enable the converter, there is a turn on delay to allow the regulator circuitry to re-establish itself. Power conversion begins with the assertion of the internal reference ready signal which occurs approximately 150s after the enable signal is received. Power Good Indicator The FB pin 6 is compared to an internal reference voltage of 0.8V to regulate the SP6654 output. The output voltage can be externally programmed within the range +1.0V to +5.0V by tying a resistor from FB to ground and FB to VOUT (pin7). See the applications section for resistor selection information. A power good indicator looks at the voltage on the feedback node. When this voltage is below 0.75V, the open drain NMOS on pin 3 sinks APPLICATION INFORMATION Inductor Selection The SP6654 uses a specially adapted minimum on-time control of regulation utilizing a precision comparator and bandgap reference. This adaptive minimum on-time control has the advantage of setting a constant current ripple for a given inductor size. From the operations section it has been shown: K Inductor Current Ripple, ILR ON L For the typical SP6654 application circuit with inductor size of 10H, and KON of 2V*sec, the SP6654 current ripple would be about 200mA, and would be fairly constant for different input and output voltages, simplifying the selection of components for the SP6654 power circuit. Other inductor values could be selected, as shown in Table 2 Components Selection. Using a larger value than 10H in an attempt to reduce output voltage ripple would reduce inductor current ripple and may not produce as stable an output ripple. For larger inductors with the SP6654, which has a peak inductor current of 1.25A, most 15H or 22H inductors would have to be larger physical sizes, limiting their use in small portable applications. Smaller values like 6.8H would more easily meet the 1.25A limit and come in small case sizes, and the increased inductor (c) Copyright 2004 Sipex Corporation Date: 05/25/04 SP6654 High Efficiency 800mA Synchronous Buck Regulator 10 APPLICATION INFORMATION: Continued current ripple of almost 300mA would produce very stable regulation and fast load transient response at the expense of slightly reduced efficiency. Other inductor parameters are important: the inductor current rating and the DC resistance. When the current through the inductor reaches the level of ISAT, the inductance drops to 70% of the nominal value. This non-linear change can cause stability problems or excessive fluctuation in inductor current ripple. To avoid this, the inductor should be selected with saturation current at least equal to the maximum output current of the converter plus half the inductor current ripple. To provide the best performance in dynamic conditions such as start-up and load transients, inductors should be chosen with saturation current close to the SP6654 inductor current limit of 1.25A. DC resistance, another important inductor characteristic, directly affects the efficiency of the converter, so inductors with minimum DC resistance should be chosen for high efficiency designs. Recommended inductors with low DC resistance are listed in table 2. Preferred inductors for on board power supplies with the SP6654 are magnetically shielded types to minimize radiated magnetic field emissions. Capacitor Selection For the 22F POSCAP with 0.04 ESR, and a 10H inductor yielding 200mA inductor current ripple ILR, the VOUT ripple would be 8mVpp. Since 8mV is a very small signal level, the actual value would probably be larger due to noise and layout issues, but this illustrates that the SP6654 output ripple can be very low indeed. To improve stability, a small ceramic capacitor, CF = 22pF should be paralleled with the feedback voltage divider RF, as shown on the typical application schematic on page 1. Another function of the output capacitance is to hold up the output voltage during the load transients and prevent excessive overshoot and undershoot. The typical performance characteristics curves show very good load step transient response for the SP6654 with the recommended output capacitance of 22F ceramic. The input capacitor will reduce the peak current drawn from the battery, improve efficiency and significantly reduce high frequency noises induced by a switching power supply. The typical input capacitor for the SP6654 is 22F ceramic, POSCAP or Aluminum Polymer. These capacitors will provide good high frequency bypassing and their low ESR will reduce resistive losses for higher efficiency. An RC filter is recommended for the VIN pin 2 to effectively reduce the noise for the ICs analog supply rail which powers sensitive circuits. This time constant needs to be at least 5 times greater than the switching period, which is calculated as 1/FLP during the CCM mode. The typical application schematic uses the values of RVIN = 10 and CVIN = 1F to meet these requirements. The SP6654 has been designed to work with very low ESR output capacitors (listed in Table 2 Component Selection) which for the typical application circuit are 22F ceramic, POSCAP or Aluminum Polymer. These capacitors combine small size, low ESR and good value. To regulate the output with low ESR capacitors of 0.01 or less, an internal ramp voltage VRAMP has been added to the FB signal to reliably trip the loop comparator (as described in the Operations section). Output ripple for a buck regulator is determined mostly by output capacitor ESR, which for the SP6654 with a constant inductor current ripple can be expressed as: VOUT (ripple) = ILR * RESR Date: 05/25/04 SP6654 High Efficiency 800mA Synchronous Buck Regulator (c) Copyright 2004 Sipex Corporation 11 APPLICATION INFORMATION: Continued INDUCTORS SURFACE MOUNT Inductor Specification Inductance (H) 10 10 10 10 6.8 6.8 6.8 6.8 Manufacturer/Part No. Sumida CDRH5D28-100 TDK RLF5018T-100MR94 Coilcraft DO1608C-103 Coilcraft LPO6013-103 Sumida CDRH5D28-6R8 TDK RLF5018T-6R8M1R1 Coilcraft DO1608C-682 Coilcraft LPO6013-103 Series R 0.048 0.056 0.160 0.300 0.081 0.47 0.130 0.200 ISAT (A) 1.30 0.94 1.10 0.70 1.12 1.10 1.20 0.60 Size LxW(mm) Ht. (mm) 5.7 x 5.5 5.6 x 5.2 6.6 x 4.5 6.0 x 5.4 4.7 x 4.5 5.6 x 5.2 6.6 x 4.5 6.0 x 5.4 3.0 2.0 2.9 1.3 3.0 2.0 2.9 1.3 Inductor Type Shielded Ferrite Core Shielded Ferrite Core Manufacturer Website sumida.com tdk.com Unshielded Ferrite Core coilcraft.com Unshielded Ferrite Core coilcraft.com Shielded Ferrite Core Shielded Ferrite Core sumida.com tdk.com Unshielded Ferrite Core coilcraft.com Unshielded Ferrite Core coilcraft.com CAPACITORS - SURFACE MOUNT Capacitor Specification Capacitance (F) 22 22 47 47 Manufacturer/Part No. TDK C3216X5R0J226M SANYO 6APA22M TDK C3225X5R0J46M SANYO 6TPA47M ESR RippleCurrent Size (max) (A) @ 45C LxW(mm) Ht. (mm) 0.002 0.040 0.002 0.040 3.00 1.90 4.00 1.90 3.2 x 1.6 7.3 x 4.3 3.2 x 1.6 6.0 x 3.2 1.6 2.0 1.6 2.8 Voltage (V) 6.3 6.3 6.3 6.3 Capacitor Type X5R Ceramic POSCAP X5R Ceramic POSCAP Manufacturer Website tdk.com sanyovideo.com tdk.com sanyovideo.com Note: Components highlighted in bold are those used on the SP6654 Evaluation Board. Table 2 Component Selection Output Voltage Program The output voltage is programmed by the external divider, as shown in the typical application circuit on page 1. First pick a value for RI that is no larger than 300K. Too large a value of RI will reduce the AC voltage seen by the loop comparator since the internal FB pin capacitance can form a low pass filter with RF in parallel with RI. The formula for RF with a given RI and output voltage is: RF = ( VOUT - 1 ) * RI 0.8V the typical 10H inductor application on 100mA is half the 200mA inductor current ripple), the output ripple frequency will be fairly constant. From the operations section, this maximum loop frequency in continuous conduction mode is: FLP 1 KON * VOUT VIN * (VIN - VOUT) Data for loop frequency, as measured from output voltage ripple frequency, can be found in the typical performance curves. Layout Considerations Output Voltage Ripple Frequency An important consideration in a power supply application is the frequency value of the output ripple. Given the control technique of the SP6654 (as described in the operations section), the frequency of the output ripple will vary when in light to moderate load in the discontinuous or PFM mode. For moderate to heavy loads greater than about 100mA inductor current ripple, (for Date: 05/25/04 Proper layout of the power and control circuits is necessary in a switching power supply to obtain good output regulation with stability and a minimum of output noise. The SP6654 application circuit can be made very small and reside close to the IC for best performance and solution size, as long as some layout techniques are taken into consideration. To avoid excessive interference between the SP6654 high frequency converter and (c) Copyright 2004 Sipex Corporation SP6654 High Efficiency 800mA Synchronous Buck Regulator 12 APPLICATION INFORMATION: Continued the other active components on the board, some rules should be followed. Refer to the typical application schematic on page 1 and the sample PCB layout shown in the following figures to illustrate how to layout a SP6654 power supply. Avoid injecting noise into the sensitive part of circuit via the ground plane. Input and output capacitors conduct high frequency current through the ground plane. Separate the control and power grounds and connect them together at a single point. Power ground plane is shown in the figure titled PCB top sample layout and connects the ground of the COUT capacitor to the ground of the CIN capacitor and then to the PGND pin 10. The control ground plane connects from pin 9 GND to ground of the CVIN capacitor and the RI ground return of the feedback resistor. These two separate control and power ground planes come together in the figure titled PCB top sample layout where SP6654 pin 9 GND is connected to pin 10 PGND. Power loops on the input and output of the converter should be laid out with the shortest and widest traces possible. The longer and narrower the trace, the higher the resistance and inductance it will have. The length of traces in series with the capacitors increases its ESR and ESL and reduces their effectiveness at high frequencies. Therefore, put the 1F bypass capacitor as close to the VIN and GND pins of the converter as possible, the 22F CIN close to the PVIN pin and the 22F output capacitor as close to the inductor as possible. The external voltage feedback network RF, RI and feedforward capacitor CF should be placed very close to the FB pin. Any noise traces like the LX pin should be kept away from the voltage feedback network and separated from it by using power ground copper to minimize EMI. SP6654EB PWRGD Figure 19. SP6654 PCB Component Sample Layout Figure 20. SP6654 PCB Top Sample Layout Figure 21. SP6654 PCB Bottom Sample Layout Date: 05/25/04 SP6654 High Efficiency 800mA Synchronous Buck Regulator (c) Copyright 2004 Sipex Corporation 13 PACKAGE: 10 PIN MSOP (ALL DIMENSIONS IN MILLIMETERS) D e1 O1 E/2 R1 R Gauge Plane O E E1 L2 Seating Plane 1 2 O1 L L1 e Pin #1 indentifier must be indicated within this shaded area (D/2 * E1/2) Dimensions in (mm) 10-PIN MSOP JEDEC MO-187 (BA) Variation MIN NOM MAX 0 0.75 0.17 0.08 0.85 3.00 BSC 4.90 BSC 3.00 BSC 0.50 BSC 2.00 BSC 0.4 0.07 0.07 0 0 0.60 0.95 0.25 10 0.80 8 15 1.1 0.15 0.95 0.27 0.23 A A1 A2 b c D E E1 e e1 L L1 L2 N R R1 O O1 (b) WITH PLATING c BASE METAL D A2 b A1 A 1 Date: 05/25/04 SP6654 High Efficiency 800mA Synchronous Buck Regulator (c) Copyright 2004 Sipex Corporation 14 PACKAGE: 10 PIN DFN Top View D e D/2 1 2 Bottom View b E/2 E K L E2 Pin 1 identifier to be located within this shaded area. Terminal #1 Index Area (D/2 * E/2) D2 A A1 A3 Side View DIMENSIONS Minimum/Maximum (mm) 10 Pin DFN (JEDEC MO-229, VEED-5 VARIATION) COMMON HEIGHT DIMENSION SYMBOL A A1 A3 b D D2 e E E2 K L MIN NOM MAX 0.80 0.90 1.00 0 0.02 0.05 0.20 REF 0.18 0.25 0.30 3.00 BSC 2.20 2.70 0.50 PITCH 3.00 BSC 1.40 1.75 0.20 0.30 0.40 0.50 10 PIN DFN Date: 05/25/04 SP6654 High Efficiency 800mA Synchronous Buck Regulator (c) Copyright 2004 Sipex Corporation 15 ORDERING INFORMATION Part Number Operating Temperature Range Top Mark Package Type SP6654EU..............................-40C to +85C.............................SP6654EU........................10 Pin MSOP SP6654EU/TR........................-40C to +85C.............................SP6654EU........................10 Pin MSOP SP6654ER..............................-40C to +85C.............................SP6654ER........................10 Pin DFN SP6654ER/TR........................-40C to +85C.............................SP6654ER........................10 Pin DFN Available in lead free packaging. To order add "-L" suffix to part number. Example: SP6654EU/TR = standard; SP6654EU-L/TR = lead free /TR = Tape and Reel Pack quantity is 2,500 for MSOP and 3,000 for DFN Corporation ANALOG EXCELLENCE Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Date: 05/25/04 SP6654 High Efficiency 800mA Synchronous Buck Regulator (c) Copyright 2004 Sipex Corporation 16 |
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